Hi folks
What’s new: A friend of mine and I are working on a replacement for the overaged and iconsistent VHDL (virtual hardware description language).
A draft of our documentation can be found here: https://blog.the-leviathan.ch/wp-content/uploads/2014/10/Towards-Type-Safety-in-asynchronous-Hardware-Description.pdf
I’ve actually been thinking about this very concept for a little while. I’d like to see your thoughts on defining the gate level logic. For example, you said that and2 is defined with 2 input bits, and one output bit, but you never describe how the input states affect the output state.
I’d also like a little bit more information on how the states help verify correctness.