During the past few months I’ve been hacking a lot on the Verilog Schematic support for Qucs, and we’ve gotten very far, with only some minor issues remaining.

While component placement now works properly, with all the orientations, positioning and the visibility of properties being exported into Verilog and read back in again, there’s still issues with the text placement of the properties, and the wire labels are missing.

Above you can see the screenshot of one of the example projects

As comparison above the screenshot of the rendering of the Verilog Schematic dump. Most of the content is now properly dumped, parsed and displayed. The only issues remaining are meta data information, specifically the preamble, text positioning and the labels of the wires.