The last couple of months I’ve been hacking on introducing the capability to store schematics as Verilog-AMS (IEEE 1364), so that I can simulate my circuits using Gnucap, in the future.

My branch with the current changes can be found on my GitHub repository: https://github.com/leviathanch/qucs/tree/read_verilog

I finally have arrived at a point, where Qucs can read in the XML based legacy schematics format and then dump it all out again into either a Legacy Schematic or a Verilog Schematic.

Now. I finally also can read in the Verilog Schematic itself and already partially render it.

Now all that remains is matching all the component types and wires during read in, to the components present in the Qucs API, and I’ll be able to directly feed my mixed signal circuits I’ll have to design for the upcoming NLNet project, into Gnucap and simulate them.